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Processor architectures for enhanced computational capability and low latency
Processor architectures for enhanced computational capability and low latency
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机译:处理器架构可增强计算能力并降低延迟
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摘要
A processor includes a compute array comprising a first plurality of compute engines serially connected along a data flow path such that data flows between successive compute engines at successive times. The first plurality of compute engines includes an initial compute engine and a final compute engine. The data flow path includes a recirculation path connecting the final compute engine to the initial compute engine with no compute engine therebetween.
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