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Vertical field effect transistor arrays including gate electrodes annularly surrounding semiconductor pillars
Vertical field effect transistor arrays including gate electrodes annularly surrounding semiconductor pillars
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机译:包括栅电极的垂直场效应晶体管阵列,该栅电极环形地围绕半导体柱
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摘要
Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.
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