首页> 外国专利> MEMORY DEVICE FOR READING AND WRITING DATA, INCLUDING SEMI-SHARED SENSE AMPLIFIER AND GLOBAL READ LINE ARCHITECTURE, AND METHOD FOR DRIVING THE MEMORY DEVICE

MEMORY DEVICE FOR READING AND WRITING DATA, INCLUDING SEMI-SHARED SENSE AMPLIFIER AND GLOBAL READ LINE ARCHITECTURE, AND METHOD FOR DRIVING THE MEMORY DEVICE

机译:用于读取和写入数据的存储器设备,包括半共享传感放大器和全局读取线体系结构,以及驱动该存储器设备的方法

摘要

memory includes a global read line and the plurality of banks. In each bank, the memory includes a sense amplifier. Discharge circuit, the plurality of detection of any one of the sense amplifiers of the amplifier when the output enable signal having a first digital logic value onto the input leads of the discharge circuit to discharge charge the global read line. In this way, the sense amplifiers share a discharge circuit. In one embodiment, the memory, the pre-charging comprises a pair of differential read line to start the reading operation. After the pre-charge, which is one of the two sense amplifier is enabled when the output of the first digital logic value, a first discharge circuit has a first discharge-charge global read line of the global read line. Which one of the two sense amplifiers are enabled when the output of the second digital logic value, the second discharge-charge circuit is a second global read line of the global read line display.
机译:存储器包括全局读取线和多个存储体。在每个存储体中,存储器包括一个读出放大器。放电电路,当将具有第一数字逻辑值的输出使能信号输出到放电电路的输入引线上以对全局读取线进行放电时,对放大器的任何一个读出放大器进行多次检测。这样,读出放大器共享一个放电电路。在存储器的一个实施例中,预充电包括一对差分读取线以开始读取操作。当第一数字逻辑值的输出被使能为两个读出放大器中的一个的预充电之后,第一放电电路具有全局读取线的第一放电充电全局读取线。当第二数字逻辑值的输出时,两个读出放大器中的哪一个被启用,第二放电-充电电路是全局读取线显示器的第二全局读取线。

著录项

  • 公开/公告号KR101090040B1

    专利类型

  • 公开/公告日2011-12-07

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20097022748

  • 发明设计人 천 즈친;정 창 호;

    申请日2008-03-19

  • 分类号G11C7/10;G11C7/06;

  • 国家 KR

  • 入库时间 2022-08-21 17:11:03

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