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MEMORY DEVICE FOR READING AND WRITING DATA, INCLUDING SEMI-SHARED SENSE AMPLIFIER AND GLOBAL READ LINE ARCHITECTURE, AND METHOD FOR DRIVING THE MEMORY DEVICE
MEMORY DEVICE FOR READING AND WRITING DATA, INCLUDING SEMI-SHARED SENSE AMPLIFIER AND GLOBAL READ LINE ARCHITECTURE, AND METHOD FOR DRIVING THE MEMORY DEVICE
memory includes a global read line and the plurality of banks. In each bank, the memory includes a sense amplifier. Discharge circuit, the plurality of detection of any one of the sense amplifiers of the amplifier when the output enable signal having a first digital logic value onto the input leads of the discharge circuit to discharge charge the global read line. In this way, the sense amplifiers share a discharge circuit. In one embodiment, the memory, the pre-charging comprises a pair of differential read line to start the reading operation. After the pre-charge, which is one of the two sense amplifier is enabled when the output of the first digital logic value, a first discharge circuit has a first discharge-charge global read line of the global read line. Which one of the two sense amplifiers are enabled when the output of the second digital logic value, the second discharge-charge circuit is a second global read line of the global read line display.
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