PURPOSE: An output enable signal generating circuit is provided to improve timing margin of a first pulse signal and a delay read pulse by performing a variable delay operation in a variably delay unit.;CONSTITUTION: A read pulse generating unit(100) generates a read pulse in response to a read command and a clock signal. A variable delay unit(200) variably delays the read pulse according to a variable delay signal and outputs the delayed read pulse as a delay read pulse. A sense amplifying unit(300) senses the delay read pulse according to a pulse signal and generates an output enable signal according to the sensed result.;COPYRIGHT KIPO 2012
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