首页> 外国专利> METHOD FOR MANUFACTURING A FLIP-CHIP SMALL OUTLINE PACKAGE CAPABLE OF REDUCING FAILURE RATE BY SIMPLIFYING MANUFACTURING PROCESS

METHOD FOR MANUFACTURING A FLIP-CHIP SMALL OUTLINE PACKAGE CAPABLE OF REDUCING FAILURE RATE BY SIMPLIFYING MANUFACTURING PROCESS

机译:通过简化制造过程来制造可降低故障率的倒装小外形包装的方法

摘要

PURPOSE: A method for manufacturing a flip- chip small outline package is provided to simply form a solder bump of high reliability by omitting a coining process of expensive costs and to reduce manufacturing costs.;CONSTITUTION: A solder resist(20) is spread on the surface of a substrate in which a copper circuit(10) is formed. The copper circuit comprises a copper pad. A solder resist opening part is formed by selectively etching the solder resist. A solder paste(40) is inserted into the solder resist opening part and a solder is formed. The solder is loaded on a plate(110) in order to be touched to the surface. A flux exhaustion process and a process flattering the solder surface are executed at the same time without an additional follow up coining process.;COPYRIGHT KIPO 2012
机译:目的:提供一种制造倒装芯片小外形封装的方法,通过省去昂贵的铸造工艺并降低制造成本,从而简单地形成高可靠性的焊料凸块;组成:在其上散布了阻焊剂(20)形成有铜电路(10)的基板表面。铜电路包括铜垫。阻焊剂开口部通过选择性地蚀刻阻焊剂而形成。将阻焊剂(40)插入阻焊剂开口部分中并形成焊料。焊料被装载在板(110)上以便被接触到表面。助焊剂耗尽工艺和使焊料表面平坦的工艺可同时执行,而无需额外的后续压印工艺。; COPYRIGHT KIPO 2012

著录项

  • 公开/公告号KR101143358B1

    专利类型

  • 公开/公告日2012-05-09

    原文格式PDF

  • 申请/专利权人 APERIO CO. LTD.;

    申请/专利号KR20100102881

  • 发明设计人 LEE SEUNG HEON;HAN JAE HYUN;

    申请日2010-10-21

  • 分类号H01L21/60;H01L23/48;

  • 国家 KR

  • 入库时间 2022-08-21 17:08:09

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号