Circuit for driving a ferroelectric swl - memory

摘要

Circuit for driving a ferroelectric swl - memory, with:– an x - according to decoder (21) for receiving and decoding of addresses x and z for activating a cells array block (23);– a global control pulse - generator (16) for providing a control pulse, as described for the purpose of writing or reading of data is required, to a signal received from the outside towards csbpad;– a locally control pulse - generator (20) for receiving the control pulse from the global control pulse - generator (16) and for providing a control signal such as, for writing and reading of data is required;– a swl - cells array block (23) for storing data;– a swl - driver (22) for driving the swl - cells array block (23) to provide control signals from the x - nachdecordierer (21) and the locally control pulse - generator (20) of the;– a y - address decoder (18) for decoding a signal received from the outside for addresses y;– a columns a control unit (24) for controlling of columns on the control signal from the locally control pulse - generator (20) and a decoded signal from the y - address decoder (18); and..