首页> 外国专利> For readout circuit, which can be described again, memory and reading-out techniques for the same

For readout circuit, which can be described again, memory and reading-out techniques for the same

机译:对于可以再次描述的读出电路,相同的存储器和读出技术

摘要

The readout circuit for rewritable memory comprising:— a control logic (sl) having an input for supplying a start signal (start) and with a plurality of outputs for providing in each case of a control signal as a function of the start signal (start),— a first terminal (21) for the switchable connection by means of a first switch (s1) with a first memory cell (140), and a second connector (22) for the switchable connection by means of a second switch (s2) with a second memory cell (130),— a with the control logic (sl), as well as with the first and the second terminal (21, 22) coupled to the readout unit (corresponding, av), with an output (23) for providing an output signal (out) as a function of a state of the first and / or the second memory cell (140, 130), and as a function of the control signals,wherein the readout circuit, in each case for itself, in a terminated and that is designed in a test mode, andthe read-out circuit for rewritable memory, in which a data bit is formed by two memory cells,..
机译:用于可擦写存储器的读出电路包括:-控制逻辑(s1),其具有用于提供启动信号(start)的输入,并且具有多个输出,用于分别根据启动信号(start)提供控制信号),-用于通过第一开关(s1)与第一存储单元(140)进行可切换连接的第一端子(21),以及用于通过第二开关(s2)进行可切换连接的第二连接器(22) )带有第二个存储单元(130),-一个带有控制逻辑(sl),以及第一和第二端子(21,22)耦合到读出单元(对应的av),输出是( 23)用于根据第一和/或第二存储单元(140、130)的状态和控制信号提供输出信号(out),其中读出电路在每种情况下用于本身,在终端并以测试模式设计,以及用于可重写存储器的读出电路,其中数据位由t构成wo存储单元..

著录项

  • 公开/公告号DE102009011255B4

    专利类型

  • 公开/公告日2012-08-23

    原文格式PDF

  • 申请/专利权人 AUSTRIAMICROSYSTEMS AG;

    申请/专利号DE20091011255

  • 发明设计人 JOHANNES FELLNER;GREGOR SCHATZBERGER;

    申请日2009-03-02

  • 分类号G11C7/06;G11C16/26;

  • 国家 DE

  • 入库时间 2022-08-21 17:05:41

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号