Method for modifying automatic topology of analog design in integrated circuits for high definition-DVD application, involves carrying-out pole-zero analysis for inserted network elements or performing gradient eigen value optimization

摘要

The method involves adding capacitance containing branches between independent circuit nodes to an output circuitry design of computerized new network elements. The amount of inserted network elements are sorted in order to extract network elements, which lead to permanent enhancement of circuitry performance and a minimum chip area demand. A pole-zero analysis for each of inserted network elements is carried out or a gradient eigen value optimization is performed. The optimization of an automatic location of intrinsic value in a complex plane is performed.