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METHOD AND SYSTEM FOR DYNAMICALLY POWER SCALING A CACHE MEMORY OF A MULTI-CORE PROCESSING SYSTEM

机译:动态功率缩放多核处理系统缓存内存的方法和系统

摘要

A system and method of power scaling cache memory (110) of a multi-core processing system includes a plurality of core processors (100), a cache memory (110) and a controller (125). The cache memory (110) includes partitioned cache (120) and shared cache (115). The shared cache (115) can be partitioned into the partitioned cache (120). Each core processor (100) is communicatively coupled to at least one corresponding partitioned cache (120) and the shared cache (100). The controller (125) is communicatively coupled to each of the core processors (100), to the partitioned cache (120), and to the shared cache (115). The controller (125) is configured to cause the at least one corresponding partitioned cache (120) to power down in response to the corresponding core processor (100) powering down. The controller (125) can also be configured to flush the cache lines of the partitioned cache (125) prior to powering down the partitioned cache (125) in response to the corresponding processor (100) powering down.
机译:一种功率缩放多核处理系统的高速缓存存储器( 110 )的系统和方法,包括多个核心处理器( 100 ),高速缓存存储器( 110 )和控制器( 125 )。缓存( 110 )包括分区缓存( 120 )和共享缓存( 115 )。共享缓存( 115 )可以分区到分区缓存( 120 )中。每个核心处理器( 100 )通信耦合到至少一个相应的分区缓存( 120 )和共享缓存( 100 )。控制器( 125 )通信耦合到每个核心处理器( 100 ),分区缓存( 120 )以及共享缓存( 115 )。控制器( 125 )配置为响应于相应的核心处理器( 100 )使至少一个相应的分区缓存( 120 )掉电。 B>)关机。控制器( 125 )也可以配置为在关闭分区缓存( 125 )之前刷新分区缓存( 125 )的缓存行>),以响应相应的处理器( 100 )关机。

著录项

  • 公开/公告号US2013246825A1

    专利类型

  • 公开/公告日2013-09-19

    原文格式PDF

  • 申请/专利权人 CHRISTOPHER JOHN SHANNON;

    申请/专利号US201113635361

  • 发明设计人 CHRISTOPHER JOHN SHANNON;

    申请日2011-03-25

  • 分类号G06F1/32;G06F12/08;

  • 国家 US

  • 入库时间 2022-08-21 16:51:56

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