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BUMP STRUCTURAL DESIGNS TO MINIMIZE PACKAGE DEFECTS

机译:缓冲结构设计以最小化包装缺陷

摘要

The mechanisms for forming bump structures enable forming bump structures between a chip and a substrate eliminating or reducing the risk of solder shorting, flux residue and voids in underfill. A lower limit can be established for a cc ratio, defined by dividing the total height of copper posts in a bonded bump structure divided by the standoff of the bonded bump structure, to avoid shorting. A lower limit may also be established for standoff the chip package to avoid flux residue and underfill void formation. Further, aspect ratio of a copper post bump has a lower limit to avoid insufficient standoff and a higher limit due to manufacturing process limitation. By following proper bump design and process guidelines, yield and reliability of chip packages may be increases.
机译:形成凸块结构的机制使得能够在芯片和衬底之间形成凸块结构,从而消除或减小了焊料短路,助焊剂残留和底部填充中的空隙的风险。可以为cc比确定下限,其通过将键合凸块结构中的铜柱的总高度除以键合凸块结构的支座来定义,以避免短路。还可以为支脚芯片封装建立下限,以避免助焊剂残留和底部填充空隙的形成。此外,铜柱凸块的纵横比具有下限值以避免产生足够的间隙,并且由于制造工艺的限制而具有较高的限值。通过遵循适当的凸块设计和工艺准则,可以提高芯片封装的良率和可靠性。

著录项

  • 公开/公告号US2013193593A1

    专利类型

  • 公开/公告日2013-08-01

    原文格式PDF

  • 申请/专利权人 JING-CHENG LIN;CHENG-LIN HUANG;

    申请/专利号US201213362913

  • 发明设计人 CHENG-LIN HUANG;JING-CHENG LIN;

    申请日2012-01-31

  • 分类号H01L23/498;H01L21/56;

  • 国家 US

  • 入库时间 2022-08-21 16:49:41

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