首页> 外国专利> BUMP STRUCTURAL DESIGNS TO MINIMIZE PACKAGE DEFECTS

BUMP STRUCTURAL DESIGNS TO MINIMIZE PACKAGE DEFECTS

机译:缓冲结构设计以最小化包装缺陷

摘要

A method of forming a chip package includes providing a chip with a plurality of first copper post bumps having a first height of copper post. The method also includes providing a substrate with a plurality of second copper post bumps having a second height of copper post. The method further includes bonding the plurality of first copper post bumps to the plurality of second copper post bumps by reflowing solder layers on the plurality of first copper post bumps and the plurality of second copper post bumps together to form a first copper post bump structure of the chip package. The first copper post bump structure has a standoff, wherein a ratio of a sum of the first height of copper post and the second height of copper post to the standoff is equal to or greater than about 0.6 and less than 1.
机译:一种形成芯片封装的方法,包括为芯片提供具有第一高度的铜柱的多个第一铜柱凸块。该方法还包括提供具有多个第二铜柱凸块的衬底,该第二铜柱凸块具有第二高度的铜柱。该方法还包括通过将多个第一铜柱凸块和多个第二铜柱凸块上的焊料层回流到一起以形成多个第一铜柱凸块结构,从而将多个第一铜柱凸块结合到多个第二铜柱凸块上。芯片封装。第一铜柱凸块结构具有支座,其中铜柱的第一高度和铜柱的第二高度的总和与支座的比率等于或大于大约0.6且小于1。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号