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STRUCTURE AND METHOD OF HIGH-PERFORMANCE EXTREMELY THIN SILICON ON INSULATOR COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTORS WITH DUAL STRESS BURIED INSULATORS
STRUCTURE AND METHOD OF HIGH-PERFORMANCE EXTREMELY THIN SILICON ON INSULATOR COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTORS WITH DUAL STRESS BURIED INSULATORS
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机译:具有双应力埋入式绝缘子的绝缘子互补金属氧化物-半金属半导体晶体管上的高性能极薄硅的结构和方法
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摘要
A method of forming a complementary metal oxide semiconductor (CMOS) device including an n-type field effect transistor (NFET) and an p-type field effect transistor (PFET) having fully silicided gates electrode in which an improved dual stress buried insulator is employed to incorporate and advantageous mechanical stress into the device channel of the NFET and PFET. The method can be imposed on a bulk substrate or extremely thin silicon on insulator (ETSOI) substrate. The device includes a semiconductor substrate, a plurality of shallow trench isolations structures formed in the ETSOI layer, NFET having a source and drain region and a gate formation, a PFET having a source and drain region, and a gate formation, an insulator layer, including a stressed oxide or nitride, deposited inside the substrate of the NFET, and a second insulator layer, including either an stressed oxide or nitride, deposited inside the substrate of the PFET.
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