首页> 外国专利> Bottom source NMOS triggered zener clamp for configuring an ultra-low voltage transient voltage suppressor (TVS)

Bottom source NMOS triggered zener clamp for configuring an ultra-low voltage transient voltage suppressor (TVS)

机译:底部源NMOS触发的齐纳钳位电路,用于配置超低压瞬态电压抑制器(TVS)

摘要

A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer thereon. The TVS device further includes a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate wherein the drain region interfaces with the body region constituting a junction diode and the drain region encompassed in the body region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode. The body regions further comprises a surface body contact region electrically connected to a body-to-source short-connection thus connecting the body region to the bottom electrode functioning as the source/emitter terminal. The gate may be shorted to the drain for configuring the BS-MOSFET transistor into a two terminal device with a gate-to-source voltage equal to a drain-to-source voltage. The drain/collector/cathode terminal disposed on top of the trench gate turns on the BS-MOSFET upon application of a threshold voltage of the BS-MOSFET thus triggering the bipolar transistor for clamping and suppressing a transient voltage substantially near a threshold voltage of the BS-MOSFET.
机译:一种低压瞬态电压抑制(TVS)器件,该器件支撑在其上支撑外延层的半导体衬底上。该TVS器件还包括底部源极金属氧化物半导体场效应晶体管(BS-MOSFET),该底部栅极金属氧化物半导体场效应晶体管包括由漏极区围绕的沟槽栅极,该漏极区包围在设置在半导体衬底的顶表面附近的主体区中,其中该漏极区与该漏极区交界。构成结型二极管的主体区域和包围在构成双极晶体管的外延层顶部上的主体区域中的漏极区域,在半导体的顶表面上设置顶电极用作漏极/集电极端子,在其上设置底电极半导体衬底的底表面用作源极/发射极。主体区域还包括表面主体接触区域,该表面主体接触区域电连接至主体-源极短路连接,从而将主体区域连接至用作源/发射极端子的底部电极。可以将栅极短接到漏极,以将BS-MOSFET晶体管配置为栅极至源极电压等于漏极至源极电压的两端设备。当施加BS-MOSFET的阈值电压时,位于沟槽栅极顶部的漏极/集电极/阴极端子会导通BS-MOSFET,从而触发双极晶体管,以钳制和抑制基本上接近于其阈值电压的瞬态电压。 BS-MOSFET。

著录项

  • 公开/公告号US8558276B2

    专利类型

  • 公开/公告日2013-10-15

    原文格式PDF

  • 申请/专利权人 MADHUR BOBDE;

    申请/专利号US20090456555

  • 发明设计人 MADHUR BOBDE;

    申请日2009-06-17

  • 分类号H01L29/02;

  • 国家 US

  • 入库时间 2022-08-21 16:47:33

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