首页> 外国专利> Bottom source NMOS triggered Zener clamp for configuring an ultra-low voltage transient voltage suppressor (TVS)

Bottom source NMOS triggered Zener clamp for configuring an ultra-low voltage transient voltage suppressor (TVS)

机译:底部源NMOS触发的齐纳钳位,用于配置超低压瞬态电压抑制器(TVS)

摘要

A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer to form a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) that comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate. The drain region interfaces with the body region constituting a junction diode. The drain region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode. The body regions further comprises a surface body contact region electrically connected to a body-to-source short-connection thus connecting the body region to the bottom electrode functioning as the source/emitter terminal.
机译:一种低电压瞬态电压抑制(TVS)装置,该装置支撑在支撑外延层的半导体衬底上,以形成底部源极金属氧化物半导体场效应晶体管(BS-MOSFET),该晶体管包括由包围在主体中的漏极区围绕的沟槽栅极设置在半导体衬底的顶表面附近的区域。漏极区与构成结二极管的主体区相接。外延层顶部的漏极区域构成双极型晶体管,其顶部电极位于半导体的顶表面,用作漏极/集电极端子,底部电极位于半导体衬底的底表面,用作源极/漏极。发射极。主体区域还包括表面主体接触区域,该表面主体接触区域电连接至主体-源极短路连接,从而将主体区域连接至用作源/发射极端子的底部电极。

著录项

  • 公开/公告号US10205017B2

    专利类型

  • 公开/公告日2019-02-12

    原文格式PDF

  • 申请/专利权人 MADHUR BOBDE;

    申请/专利号US201314037205

  • 发明设计人 MADHUR BOBDE;

    申请日2013-09-25

  • 分类号H01L29/78;H01L29/66;H01L29/70;H01L29/732;H01L21/8249;H01L27/07;

  • 国家 US

  • 入库时间 2022-08-21 12:13:21

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