Self-aligned III-V field effect transistor (FET), integrated circuit (IC) chip with self-aligned III-V FETS and method of manufacture

摘要

Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered semiconductor wafer preferably includes a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). Portions of the buried layer are converted to dielectric material, e.g., Aluminum Oxide (AlO), at least beneath FET source/drain regions. The converted dielectric material may extend completely under the FET. Source/drain contacts are formed to FETs above the dielectric material in the buried layer.