首页>
外国专利>
Insertion of faults in logic model used in simulation
Insertion of faults in logic model used in simulation
展开▼
机译:在仿真中使用的逻辑模型中插入故障
展开▼
页面导航
摘要
著录项
相似文献
摘要
A method of selecting fault candidates based on the physical layout of an Integrated Circuit (IC) layout, that includes, identifying failing observation points in an IC layout, determining the failing observation points proximity geometry in the IC circuit layout, determining if a proximity criteria for the failing observation points is met, and identifying faults associated with the failing observation points that meet the proximity criteria; and including the identified faults in a fault candidate set.
展开▼