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Method, system, and apparatus for adjusting local and global pattern density of an integrated circuit design

机译:用于调整集成电路设计的局部和全局图案密度的方法,系统和装置

摘要

An integrated circuit (IC) design method providing a circuit design layout having a plurality of functional blocks disposed a distance away from each other; identifying a local pattern density to an approximate dummy region, on the circuit design layout, within a predefined distance to one of the functional blocks; performing a local dummy insertion to the approximate dummy region according to the local pattern density; repeating the identifying and performing to at least some other of the functional blocks; and implementing a global dummy insertion to a non-local dummy region according to a global pattern density.
机译:一种集成电路(IC)设计方法,提供一种电路设计布局,该电路设计布局具有彼此隔开一定距离设置的多个功能块;在电路设计布局上,在到功能块之一的预定距离内,识别局部图形密度到近似虚设区域;根据局部图案密度对近似虚拟区域进行局部虚拟插入;重复对至少一些其他功能块的识别和执行;根据全局图案密度,实现对非局部虚拟区域的全局虚拟插入。

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