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Implementing single bit redundancy for dynamic SRAM circuit with any bit decode
Implementing single bit redundancy for dynamic SRAM circuit with any bit decode
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机译:通过任何位解码为动态SRAM电路实现单位冗余
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摘要
A method and a dynamic Static Random Access Memory (SRAM) circuit for implementing single bit redundancy with any bit decode, and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a plurality of bitline columns and a pair of redundancy columns respectively coupled to a respective merged bit column select and redundancy steering multiplexer. Each merged bit column select and redundancy steering multiplexer receives a respective select signal input. A select signal generation circuit receives a redundancy steering signal and a respective one-hot bit select signal, generating the respective select signal input.
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