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Latch circuit, flip-flop having the same and data latching method
Latch circuit, flip-flop having the same and data latching method
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机译:锁存电路,具有该锁存电路的触发器和数据锁存方法
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摘要
A latch circuit includes a first tri-state inverter configured to invert an input voltage in response to a pulse and to output the inverted voltage to a first node, a second tri-state inverter connected between the first node and a second node and to invert a voltage of the second node in response to an inverted pulse being an inverted version of the pulse, and a variable inversion unit connected between the first node and the second node. The variable inversion unit adjusts a logical threshold value according to a logical value corresponding to a voltage of the first node and inverts a voltage of the first node based upon the adjusted logical threshold value, the logical threshold value indicating a voltage for discriminating the logical value.
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