system for synchronizing the operation of a circuit with a control signal, and corresponding integrated circuit

摘要

A system for synchronizing operation of a circuit (FSM1) with a control signal (sync) comprising a plurality of synchronization flip-flops (20) operating in cascade for receiving at input a control signal (sync) to be synchronized and supplying at output a corresponding control signal synchronized with a clock signal (CLK1). The circuit (FSM1) is configured as a finite-state machine (FSM1) cadenced by the clock signal (CLK1) and comprises a plurality of state flip-flops (24) for storing the current state of the finite-state machine (FSM1). The finite-state machine (FSM1) comprises at least one first state in which the finite-state machine (FSM1) is configured for: - remaining in the first state encoded with a first bit sequence if the synchronized control signal has a first logic value, and - proceeding to a second state encoded with a second bit sequence if the synchronized control signal has a second logic value, where the first bit sequence and the second bit sequence differ for the value of a single bit. In this way, the last synchronization flip-flop (20) can be obtained via the state flip-flop (24) in which said single bit is stored.