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VARIABLE CAPACITANCE STRUCTURE FOR CONTROLLING TIME DELAY IN A DIGITAL DESIGN
VARIABLE CAPACITANCE STRUCTURE FOR CONTROLLING TIME DELAY IN A DIGITAL DESIGN
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机译:数字设计中用于控制时间延迟的可变电容结构
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摘要
PURPOSE: A variable capacitance structure is provided to obtain valid capacitance by receiving different signals through a each second stage of a plurality of MOS(metal oxide semiconductor) capacitors.;CONSTITUTION: A capacitance structure is formed(1105). Each MOSCAP(MOS capacitor) is formed respectively as a PMOSCAP(P-channel MOSCAP) or an NMOSCAP(N-channel MOSCAP) with a PMOS(P-channel MOS) transistor or an NMOS transistor(N-channel MOS). Each signal is provided in a binary value(1110). The K number of binary values is corresponded to the K number of signals. Valid capacitance is obtained in a node Ceff(1115). It is determined whether or not the valid capacitance is a desired capacitance(1120). It is determined as the valid capacitance as the desired capacitance(1125).;COPYRIGHT KIPO 2013;[Reference numerals] (1105) Forming a capacitance structure; (1110) Providing each signal in a binary value; (1115) Obtaining a valid capacitance; (1120) Desired capacitance(Ceff)?; (1125) End
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