DUTY RATIO CALIBRATION CIRCUIT PROVIDING A FIXED CLOCK SIGNAL WITH A DUTY RATIO OF 50:50

摘要

PURPOSE: A duty ratio calibration circuit is provided to calibrate a duty ratio of a clock signal by using an asymmetric buffer part receiving a clock signal.;CONSTITUTION: An asymmetric buffer part(14) receives a clock signal. The asymmetric buffer part adjusts a duty ratio of the clock signal in response to control signals. A clock generation circuit(16) is connected to the asymmetric buffer part. The clock generation circuit detects a duty ratio of the clock signal. A control part(18) generates control signals according to a duty ratio of the detected clock signal. Operation of the control part is recorded in a recording medium as a program readable by a computer. The asymmetric buffer part includes multiple PMOS transistors selectively turned on in response to first control signals and multiple NMOS transistors selectively turned on in response to second control signals.;COPYRIGHT KIPO 2013