PARALLEL TEST CIRCUIT AND PARALLEL TEST METHOD OF A SEMICONDUCTOR MEMORY DEVICE CAPABLE OF DETERMINING THE NORMALITY OF A MEMORY CELL

摘要

PURPOSE: A parallel test circuit and parallel test method of a semiconductor memory device are provided to shorten a memory cell test time by simultaneously testing sub-banks included in one bank.;CONSTITUTION: A first memory bank (100) includes a first sub-bank (10), a second sub-bank (20), a compression part (30), and an output part (40). A global line and a test global line of the second sub-bank are composed of a plurality of lines. The compression part compares and compresses each data loaded in the global lines and data loaded in the test global lines of the second sub-bank and outputs a compression result. The output part generates a test output signal in response to a strobe signal and the compression result and outputs the test output signal to an I/O pad.;COPYRIGHT KIPO 2013;[Reference numerals] (10) First sub-bank; (100) First memory bank; (20) Second sub-bank; (30) Compression part; (40) Output part