首页> 外国专利> Method for manufacturing integrated circuit for e.g. P-channel complementary MOS transistor, involves producing recess in active region by etching process, and forming semiconductor alloy by performing epitaxial growth process

Method for manufacturing integrated circuit for e.g. P-channel complementary MOS transistor, involves producing recess in active region by etching process, and forming semiconductor alloy by performing epitaxial growth process

机译:用于制造例如集成电路的集成电路的方法P沟道互补MOS晶体管,涉及通过蚀刻工艺在有源区中产生凹槽,以及通过执行外延生长工艺形成半导体合金

摘要

The method involves forming a buried etch stop layer (210a) in a crystalline active region of a transistor e.g. P-channel complementary MOS (CMOS) transistor. A recess is produced in the crystalline active region by carrying-out an etching process e.g. wet-chemical etching process, where the recess possesses a crystallographic anisotropic ablation rate during part of the etching process. The buried etch stop layer is used as an etch stop. A deformation-inducing semiconductor alloy is formed in the recess by performing a selective epitaxial growth process. An independent claim is also included for a semiconductor component.
机译:该方法涉及在例如晶体管的晶体有源区域中形成掩埋的蚀刻停止层(210a)。 P沟道互补MOS(CMOS)晶体管。通过执行蚀刻工艺,例如,在晶体活性区域中产生凹陷。湿化学蚀刻工艺,其中在部分蚀刻工艺中,凹槽具有晶体学各向异性的烧蚀速率。掩埋的蚀刻停止层用作蚀刻停止。通过执行选择性外延生长工艺,在凹槽中形成引起变形的半导体合金。对于半导体组件也包括独立权利要求。

著录项

  • 公开/公告号DE102011079833A1

    专利类型

  • 公开/公告日2013-01-31

    原文格式PDF

  • 申请/专利权人 GLOBALFOUNDRIES INC.;

    申请/专利号DE20111079833

  • 发明设计人 OSTERMAY INA;KRONHOLZ STEPHAN;OTT ANDREAS;

    申请日2011-07-26

  • 分类号H01L21/336;H01L29/78;H01L21/265;H01L21/3065;

  • 国家 DE

  • 入库时间 2022-08-21 16:22:24

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