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LOGICAL SIMULATION DEVICE, LOGICAL SIMULATION PROGRAM, INTEGRATED CIRCUIT, AND COMPOSITE INTEGRATED CIRCUIT

机译:逻辑仿真设备,逻辑仿真程序,集成电路和复合集成电路

摘要

PROBLEM TO BE SOLVED: To facilitate design of an integrated circuit which can surely reset a plurality of basic components included in the integrated circuit.;SOLUTION: A logical simulation device reads a plurality of basic component macros described as operation models for basic components. The basic component comprises: a plurality of flip-flops 7120 which include reset output terminals for outputting signals indicating whether the basic component is in a reset state or a reset released state; and an output unit 7230 which outputs a reset state signal when the signals output from the respective reset output terminals of the plurality of flip-flops indicate that the basic component is in the reset state. The logical simulation device configures a logical model of an integrated circuit on the basis of a net list and the plurality of basic component macros, executes logical simulation of the integrated circuit by using the logical model, and outputs output data corresponding to input data.;COPYRIGHT: (C)2014,JPO&INPIT
机译:解决的问题:为了促进集成电路的设计,该集成电路可以确定地重置集成电路中包括的多个基本组件。解决方案:逻辑仿真设备读取多个基本组件宏,这些宏被描述为基本组件的操作模型。基本部件包括:多个触发器7120,其包括复位输出端子,用于输出指示基本部件处于复位状态还是复位释放状态的信号;输出单元7230,当从多个触发器的各个复位输出端子输出的信号表示基本成分处于复位状态时,输出复位状态信号。逻辑仿真设备基于网表和多个基本组成部分宏来配置集成电路的逻辑模型,并使用该逻辑模型执行集成电路的逻辑仿真,并输出与输入数据相对应的输出数据。版权:(C)2014,JPO&INPIT

著录项

  • 公开/公告号JP2014146108A

    专利类型

  • 公开/公告日2014-08-14

    原文格式PDF

  • 申请/专利权人 FUJITSU SEMICONDUCTOR LTD;

    申请/专利号JP20130013265

  • 发明设计人 KOSUGI NAOTO;

    申请日2013-01-28

  • 分类号G06F1/24;G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-21 16:19:34

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