HIERARCHICALLY STRUCTURED ARITHMETIC CIRCUIT

摘要

PROBLEM TO BE SOLVED: To generate a CRC code at high speed in fewer clocks even from input data of more bits.;SOLUTION: A hierarchically structured arithmetic circuit includes: two unit arithmetic circuits 10C each for dividing sixteen-bit parallel input data by a seventh-order irreducible polynomial and outputting the remainder as a parallel eight-bit CRC code; one unit arithmetic circuit 10D for dividing a total of sixteen-bit CRC code output from the two unit arithmetic circuit 10C by the seventh-order irreducible polynomial and outputting the remainder as a parallel eight-bit CRC code; and a register 20 for holding the parallel eight-bit CRC code output from the one unit arithmetic circuit 10D.;COPYRIGHT: (C)2014,JPO&INPIT