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Method for reducing Fermi level pinning in non-silicon channel MOS devices
Method for reducing Fermi level pinning in non-silicon channel MOS devices
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机译:减少非硅沟道MOS器件中费米能级钉扎的方法
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摘要
A method to reduce (avoid) Fermi Level Pinning (FLP) in high mobility semiconductor compound channel such as Ge and III-V compounds (e.g. GaAs or InGaAs) in a Metal Oxide Semiconductor (MOS) device. The method is using atomic hydrogen which passivates the interface of the high mobility semiconductor compound with the gate dielectric and further repairs defects. The methods further improves the MOS device characteristics such that a MOS device with a quantum well is created.
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