Semiconductor device design method and the shift register and the shift register circuit

摘要

PROBLEM TO BE SOLVED: To provide a transistor whose overlap capacitance can be reduced, thereby obtaining a shift register circuit which prevents a reduction in a power supply voltage margin.;SOLUTION: An NMOS transistor Q3 to be inserted between a second power supply terminal S2 and a node N1 is configured by using four NMOS transistors Q3a-Q3d connected in parallel so that source and drain electrodes (source electrodes 4 of the NMOS transistors Q3a-Q3d, and drain electrodes 3 of the NMOS transistors Q3b and Q3c) other than drain electrodes of transistor terminal portions (drain electrodes 3 of the NMOS transistors Q3a and Q3d) can be reliably formed on an a-Si semiconductor region 2 formed on a gate electrode 1. Moreover, a formation width L of the source electrode 4 connected to the node N1 is caused to be smaller than the sum of gate-source electrode overlap widths a1 and a2 in a region B of the transistor terminal portion.;COPYRIGHT: (C)2011,JPO&INPIT