MARGIN FREE PVT TOLERANT FAST SELF-TIMED SENSE AMPLIFIER RESET CIRCUIT

摘要

In described embodiments, a circuit for providing a margin free PVT tolerant fast self-timed sense amplifier reset includes a sense amplifier coupled between a complementary pair of first and second bitlines in a memory cell, a first and second PMOS drivers connected to internal nodes of the sense amplifier, respectively, and outputting a first and second output signals, wherein the second output signal is inverted by an inverter to form an inverted output signal, a read detect block receiving the first and inverted output signals and generating a transition detect signal that is latched by a cross-coupled inverters and employed to generate a sense amplifier enable signal with a global sense amplifier enable signal, and a push-pull logic formed by a NMOS and a PMOS in series to generate an output of the circuit.