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SCAN TEST CIRCUITRY WITH CONTROL CIRCUITRY CONFIGURED TO SUPPORT A DEBUG MODE OF OPERATION
SCAN TEST CIRCUITRY WITH CONTROL CIRCUITRY CONFIGURED TO SUPPORT A DEBUG MODE OF OPERATION
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机译:带有控制电路的扫描测试电路,该电路配置为支持调试模式的操作
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摘要
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains each having a plurality of scan cells. The scan test circuitry further comprises control circuitry comprising first switching elements configured to control selective application of respective scan input signals to respective scan inputs of respective ones of the plurality of scan chains and second switching elements configured to control selective application of a shift enable signal to respective shift enable inputs of the respective ones of the plurality of scan chains. By appropriate control of the switching elements using test data register bits or other scan chain specific control signals, one or more debug modes can be supported by the scan test circuitry of the integrated circuit.
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