Geometric regularity in fin-based multi-gate transistors of a standard cell library

摘要

A method of optimizing a layout of an integrated circuit formed using fin-based cells of a standard cell library is provided. The method includes arranging cell rows of different track heights having standard cells. For each cell row, each of the standard cells includes sub-cell rows with sub-cells of one or more types. The sub-cells are interchangeable with one another to modify a device characteristic of the standard cell. The method also includes evaluating the integrated circuit to determine whether a performance metric of the integrated circuit has been satisfied. The method also includes identifying one or more standard cells to modify a device characteristic of the standard cell for satisfying the performance metric of the integrated circuit. The method further includes modifying the one or more standard cells until the performance metric of the integrated circuit is satisfied.