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Method for non-volatile memory with background data latch caching during read operations
Method for non-volatile memory with background data latch caching during read operations
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机译:在读取操作期间具有后台数据锁存器缓存的非易失性存储器的方法
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摘要
Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a read operation. A read caching scheme is implemented for memory cells where more than one bit is sensed together, such as sensing all of the n bits of each memory cell of a physical page together. The n-bit physical page of memory cells sensed correspond to n logical binary pages, one for each of the n-bits. Each of the binary logical pages is being output in each cycle, while the multi-bit sensing of the physical page is performed every nth cycles.
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