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Method for generating post-OPC layout in consideration of top loss of etch mask layer
Method for generating post-OPC layout in consideration of top loss of etch mask layer
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机译:考虑到蚀刻掩模层的顶部损耗的产生opc后布局的方法
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摘要
A method of forming a semiconductor circuit includes receiving target layout. An optical proximity correction process is performed on the target layout data to generate a post-OPC layout. A patterning process is performed using the post-OPC layout. The post-OPC layout may be adjusted to compensate for a top loss of an etch mask layer.
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