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NMOS buffer for high-speed low-resolution current steering digital-to-analog converters

机译:NMOS缓冲器,用于高速低分辨率电流控制数模转换器

摘要

The present disclosure provides techniques for using an NMOS field effect transistor-based buffer to buffer a pair of complementary digital signals and output a pair of equivalently fast rising and fast falling complementary signals to simultaneously drive a differential pair of PMOS transistors of a unit cell that output an analog signal for a current steering DAC. Accordingly, a DAC comprises a latch circuit and a unit cell circuit. The latch circuit includes an NMOS field effect transistor-based buffer and is capable of receiving a first digital signal and a clock signal and outputting a second digital signal through the NMOS field effect transistor-based buffer according to the clock signal. The second digital signal is associated with the first digital signal. The unit cell circuit, coupled to the latch circuit, receives the second digital signal and outputs an analog signal representative of the first digital signal.
机译:本公开提供了用于使用基于NMOS场效应晶体管的缓冲器来缓冲一对互补数字信号并输出​​一对等效地快速上升和快速下降的互补信号以同时驱动单位单元的差分对的PMOS晶体管对的技术。输出用于电流控制DAC的模拟信号。因此,DAC包括锁存电路和单位单元电路。锁存电路包括基于NMOS场效应晶体管的缓冲器,并且能够接收第一数字信号和时钟信号,并且能够根据时钟信号通过基于NMOS场效应晶体管的缓冲器输出第二数字信号。第二数字信号与第一数字信号相关联。耦合到锁存电路的单位单元电路接收第二数字信号并输出​​代表第一数字信号的模拟信号。

著录项

  • 公开/公告号US8610609B2

    专利类型

  • 公开/公告日2013-12-17

    原文格式PDF

  • 申请/专利权人 BERNARD GINETTI;

    申请/专利号US201213423061

  • 发明设计人 BERNARD GINETTI;

    申请日2012-03-16

  • 分类号H03M1/00;

  • 国家 US

  • 入库时间 2022-08-21 16:00:21

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