首页> 外国专利> NMOS buffer for high-speed low-resolution current steering digital-to-analog converters

NMOS buffer for high-speed low-resolution current steering digital-to-analog converters

机译:NMOS缓冲器,用于高速低分辨率电流控制数模转换器

摘要

The present disclosure provides techniques for using an NMOS field effect transistor-based buffer (120) to buffer a pair of complementary digital signals (QI, QBI) and output a pair of equivalently fast rising and fast falling complementary signals (Q, QB) to simultaneously drive a differential pair of PMOS transistors (212, 214) of a unit cell (210) that output an analog signal for a current steering DAC. Accordingly, a DAC (200) comprises a latch circuit (100) and a unit cell circuit (210). The latch circuit (100) includes an NMOS field effect transistor-based buffer (120) and is capable of receiving a first digital signal (D) and a clock signal (E) and outputting a second digital signal through the NMOS field effect transistor-based buffer (120) according to the clock signal. The second digital signal is associated with the first digital signal. The unit cell circuit (210), coupled to the latch circuit (100), receives the second digital signal (Q, QB) and outputs an analog signal (outp, putn) representative of the first digital signal (D).
机译:本公开提供了用于使用基于NMOS场效应晶体管的缓冲器(120)来缓冲一对互补数字信号(QI,QBI)并且将一对等效快速上升和快速下降互补信号(Q,QB)输出到的技术。同时驱动单位单元(210)的一对差分PMOS晶体管(212、214),它们输出用于电流控制DAC的模拟信号。因此,DAC(200)包括锁存电路(100)和单位单元电路(210)。锁存电路(100)包括一个基于NMOS场效应晶体管的缓冲器(120),并且能够接收第一数字信号(D)和时钟信号(E),并通过NMOS场效应晶体管输出第二数字信号,根据该时钟信号的高电平缓冲器(120)。第二数字信号与第一数字信号相关联。耦合到锁存电路(100)的单位单元电路(210)接收第二数字信号(Q,QB),并输出代表第一数字信号(D)的模拟信号(outp,putn)。

著录项

  • 公开/公告号EP2568603B1

    专利类型

  • 公开/公告日2018-09-12

    原文格式PDF

  • 申请/专利权人 MSTAR SEMICONDUCTOR INC;

    申请/专利号EP20120169762

  • 发明设计人 GINETTI BERNARD;

    申请日2012-05-29

  • 分类号H03K3/356;H03K5/00;H03M1/66;H03K5/151;

  • 国家 EP

  • 入库时间 2022-08-21 13:20:20

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