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NMOS buffer for high-speed low-resolution current steering digital-to-analog converters
NMOS buffer for high-speed low-resolution current steering digital-to-analog converters
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机译:NMOS缓冲器,用于高速低分辨率电流控制数模转换器
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摘要
The present disclosure provides techniques for using an NMOS field effect transistor-based buffer (120) to buffer a pair of complementary digital signals (QI, QBI) and output a pair of equivalently fast rising and fast falling complementary signals (Q, QB) to simultaneously drive a differential pair of PMOS transistors (212, 214) of a unit cell (210) that output an analog signal for a current steering DAC. Accordingly, a DAC (200) comprises a latch circuit (100) and a unit cell circuit (210). The latch circuit (100) includes an NMOS field effect transistor-based buffer (120) and is capable of receiving a first digital signal (D) and a clock signal (E) and outputting a second digital signal through the NMOS field effect transistor-based buffer (120) according to the clock signal. The second digital signal is associated with the first digital signal. The unit cell circuit (210), coupled to the latch circuit (100), receives the second digital signal (Q, QB) and outputs an analog signal (outp, putn) representative of the first digital signal (D).
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