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Synthesizing VHDL multiple wait FSMS into RT level FSMS by preprocessing
Synthesizing VHDL multiple wait FSMS into RT level FSMS by preprocessing
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机译:通过预处理将VHDL多等待FSMS合成为RT级FSMS
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摘要
Preprocessing parallel sequences of “wait” statements and synthesizing these multiple “wait” statements to construct support for RTL tools. This is accomplished by preprocessing a VHDL process with multiple wait statements (referred to as BehFSM) into an equivalent register transfer.
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