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Multi phase clock signal generator, signal phase adjusting loop utilizing the multi phase clock signal generator, and multi phase clock signal generating method
Multi phase clock signal generator, signal phase adjusting loop utilizing the multi phase clock signal generator, and multi phase clock signal generating method
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机译:多相时钟信号发生器,利用该多相时钟信号发生器的信号相位调整环以及多相时钟信号产生方法
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摘要
A multi-phase clock signal generator, comprising: a ring phase shifting loop, including a plurality of controllable delay cells, for generating output clock signals having different phases via the controllable delay cells according to a input clock signal, wherein delay amount of the controllable delay cells are determined by a biasing voltage; a phase skew detecting circuit, for computing phase differences of the output clock signals to generate a phase skew detecting signal; and a biasing circuit, for providing the biasing voltage according to the phase skew detecting signal. The above-mentioned ring phase shifting loop can operate independently from the multi-phase clock signal generator, without receiving the biasing voltage, for phase-shifting a input clock signal to generate output clock signals with different phases, wherein the output clock signals are respectively output at different output terminals respectively located between the phase shifting units.
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