DYNAMICALLY RECONFIGURABLE MULTISTAGE PARALLEL SINGLE-INSTRUCTION MULTI-DATA ARRAY PROCESSING SYSTEM

摘要

Disclosed is a dynamically reconfigurable multistage parallel single-instruction multiple-data array processing system, comprising a pixel-level parallel processing element (PE) array and a row-parallel row processor (RP) array, wherein the PE array mainly completes a linear operation part suitable for being parallelly executed as a full pixel in low-level and middle-level image processing, and the RP array completes operations suitable for being completed in a row-parallel mode or relatively complicated non-linear operations in low-level and middle-level processing. Particularly, the PE array also can be dynamically reconfigured into a two-dimensional self-organizing mapping (SOM) neural network at an extremely low performance and area consumption, and the neural network can realize a high-level image processing function, such as high-speed parallel online training and feature identification under the cooperation of the RP, thoroughly overcoming the defect that a pixel-level parallel processing array in an existing programmable vision chip and parallel vision processor cannot be used for high-level image processing, and promoting the realization of a low cost, low power consumption and intelligent portable high-speed real-time on-chip vision image system with complete function.