Min-sum based hybrid non-binary low-density parity check (LDPC) decoder

摘要

Systems, methods, devices, circuits for a min-sum based hybrid non-binary low density parity check decoder are disclosed. A data processing system (200) is disclosed including an apparatus for decoding data having a variable node processor (202) and a check node processor (204). The variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages and to calculate checksums based on variable node to check node messages. The variable node processor and the check node processor operate on different Galois fields GF(q) and GF(p), which requires transformations (242, 262) of the messages exchanged between the check and variable node processors from GF(q) to GF(p) and vice versa.