Dual-Channel ADC minimizing input sampling-time mismatch

摘要

PURPOSE: A dual channel analog to digital converter (ADC) is provided to sample an input signal by using a sampling clock of each channel by solving a mismatching problem. CONSTITUTION: An ADC comprises an SHA (110), an MDAC (120-130), an SHA sampling clock generator, and a flash ADC (140-160). An input end of the SHA or the MDAC constructs an X channel and a Y channel. The X channel shares an amplifier with the Y channel. The SHA sampling clock generator generates the sampling clock of the X channel and the sampling clock of the Y channel. The sampling clock of the X channel and the sampling clock of the Y channel are synchronized with a falling edge of a reference clock. A delay control circuit controls the delay time of a reference clock synchronizing with the SHA sampling clock generating the SHA sampling clock generator used in a digital correction circuit.