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Vertical pillar transistor, DRAM device including the same, method for forming the vertical pillar transistor and method for forming a semiconductor layer

机译:垂直柱状晶体管,包括该垂直柱状晶体管的DRAM器件,形成垂直柱状晶体管的方法和形成半导体层的方法

摘要

In a semiconductor device and associated methods, the semiconductor device includes a substrate, an insulation layer on the substrate, a conductive structure on the insulation layer, the conductive structure including at least one metal silicide film pattern, a semiconductor pattern on the conductive structure, the semiconductor pattern protruding upwardly from the conductive structure, a gate electrode at least partially enclosing the semiconductor pattern, the gate electrode being spaced apart from the conductive structure, a first impurity region at a lower portion of the semiconductor pattern, and a second impurity region at an upper portion of the semiconductor pattern.
机译:在半导体器件及其相关方法中,该半导体器件包括衬底,在衬底上的绝缘层,在绝缘层上的导电结构,该导电结构包括至少一个金属硅化物膜图案,在该导电结构上的半导体图案,半导体图案从导电结构向上突出;栅电极至少部分地包围半导体图案;栅电极与导电结构间隔开;半导体图案下部的第一杂质区;第二杂质区在半导体图案的上部。

著录项

  • 公开/公告号KR101394157B1

    专利类型

  • 公开/公告日2014-05-14

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20080032816

  • 申请日2008-04-08

  • 分类号H01L27/108;H01L21/8242;H01L21/336;H01L29/78;

  • 国家 KR

  • 入库时间 2022-08-21 15:40:58

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