A method and structure for low-resistance source and drain regions in a process sequence with spare-metal-gate

摘要

In one embodiment, a method is provided in the providing a structure, which contains a semiconductor substrate (12) with at least a region (14) of a unit as well as a doped semiconductor layer, which is located on an upper side of the semiconductor substrate in the at least one region of the unit is located. According to the provision of the structure, a victim-gate area (28) having a side walls of the spacers (34) located on a top side of the doped semiconductor layer is formed. Subsequently, a planarizing dielectric material (36) is formed, and the victim-gate area (28) is removed, in order to an opening (38), which form a proportion of the doped semiconductor layer exposes. The opening is up to an upper side of the semiconductor substrate (20), and subsequently, a tempering process is carried out, of the out-diffusion of dopants from the remaining portions of the doped semiconductor layer is produced, whereby a source region (40) and a drain region (42) in proportions of the semiconductor substrate are formed, which, while the remaining portions of the doped semiconductor layer are. Then, a gate dielectric (46) having a high k and a metal gate (48) in the expanded opening formed.