Alternative 3D stacking scheme for DRAMs atop GPUs

摘要

A three dimensional integrated circuit chip (3D IC) package 200 includes a logic chip 204 such as a graphics processing unit (GPU) disposed between a first supporting substrate 216a and a second supporting substrate 216b, and a plurality of memory stacks 202a-f which may be stacked DRAM devices is disposed on a surface of the logic chip 204. The logic chip may be separated from the supporting substrates by a distance such that at least a portion of the memory stacks at one side of the logic chip which extend outwards past a side edge of the logic chip 214a is supported by the first supporting substrate, and at least a portion of the memory stacks which extend outwards past a second side edge of the logic chip 214b opposite to the first side edge, is supported by the second supporting substrate. The area of the supporting substrates not covered by edge columns of memory stacks may be used to conduct heat generated by the logic chip to a heat sink in use. Each of the devices 2051-2054 in a stack is electrically connected using vertical through silicon vias (TSVs) 208 that penetrate the devices.