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METHODOLOGY OF FORMING CMOS GATES ON THE SECONDARY AXIS USING DOUBLE-PATTERNING TECHNIQUE
METHODOLOGY OF FORMING CMOS GATES ON THE SECONDARY AXIS USING DOUBLE-PATTERNING TECHNIQUE
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机译:使用双拼技术在二次轴上形成CMOS门的方法
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摘要
An integrated circuit containing core transistors and I/O transistors oriented perpendicular to the core transistors is formed by exposing a gate etch mask layer stack through a gate pattern photomask including core transistor gates and oversized I/O transistor gates. Core transistor gate lengths are defined by the gate pattern photomask. A first gate hardmask etch process removes the gate hardmask layer in exposed areas. The process continues with exposing a gate trim mask layer stack through a gate trim photomask. I/O gate lengths are defined by the gate trim photomask. A second gate hardmask etch process removes the gate hardmask layer in exposed areas. A gate etch operation removes polysilicon exposed by the gate hardmask layer to form gates for the core transistors and I/O transistors. The integrated circuit may also include I/O transistors oriented parallel to the core transistors, with gate lengths defined by the gate pattern photomask.
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