首页> 外国专利> TECHNIQUE FOR REDUCING PLASMA-INDUCED ETCH DAMAGE DURING THE FORMATION OF VIAS IN INTERLAYER DIELECTRICS BY MODIFIED RF POWER RAMP-UP

TECHNIQUE FOR REDUCING PLASMA-INDUCED ETCH DAMAGE DURING THE FORMATION OF VIAS IN INTERLAYER DIELECTRICS BY MODIFIED RF POWER RAMP-UP

机译:通过改进的RF功率减小层间介电体中的通孔形成过程中减少等离子体诱发的沟槽损伤的技术

摘要

When performing plasma assisted etch processes for patterning complex metallization systems of microstructure devices, the probability of creating plasma-induced damage, such as arcing, may be reduced or substantially eliminated by using a superior ramp-up system for the high frequency power and the low frequency power. To this end, the high frequency power may be increased at a higher rate compared to the low frequency power component, wherein, additionally, a time delay may be applied so that, at any rate, the high frequency component reaches its target power level prior to the low frequency component.
机译:当执行等离子辅助蚀刻工艺以对微结构器件的复杂金属化系统进行构图时,可以通过使用用于高频功率和低功率的高级加速系统来降低或基本上消除产生等离子引起的损坏(例如电弧)的可能性。频率功率。为此,与低频功率分量相比,可以以更高的速率增加高频功率,其中,此外,可以施加时间延迟,以便无论如何,高频分量在到达之前达到其目标功率水平。低频分量。

著录项

  • 公开/公告号US2015200131A1

    专利类型

  • 公开/公告日2015-07-16

    原文格式PDF

  • 申请/专利权人 GLOBALFOUNDRIES INC.;

    申请/专利号US201514671027

  • 发明设计人 MOHAMMED RADWAN;MATTHIAS ZINKE;

    申请日2015-03-27

  • 分类号H01L21/768;H01L23/532;H01L23/522;H01L21/311;

  • 国家 US

  • 入库时间 2022-08-21 15:26:07

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