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DISTRIBUTING MULTIPLEXING LOGIC TO REMOVE MULTIPLEXOR LATENCY ON THE OUTPUT PATH FOR VARIABLE CLOCK CYCLE, DELAYED SIGNALS
DISTRIBUTING MULTIPLEXING LOGIC TO REMOVE MULTIPLEXOR LATENCY ON THE OUTPUT PATH FOR VARIABLE CLOCK CYCLE, DELAYED SIGNALS
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机译:分配多路逻辑以消除可变时钟周期,延迟信号输出路径上的多路延迟
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摘要
A controller sets a selector register of programmable delay signal logic is to a value equal to a required number of clock cycles of delay for signals output from an integrated circuit to an external memory. The controller controls a selection of additional logic along the output path to perform on the delayed signal within a clock cycle without any latency added to the output path by delay signal logic outputting the delayed signal. The controller waits required number of clock cycles after setting the selector register before using the delayed signal output by the delay signal logic onto an output path.
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