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HYBRID ON-CHIP CLOCK CONTROLLER TECHNIQUES FOR FACILITATING AT-SPEED SCAN TESTING AND SCAN ARCHITECTURE SUPPORT
HYBRID ON-CHIP CLOCK CONTROLLER TECHNIQUES FOR FACILITATING AT-SPEED SCAN TESTING AND SCAN ARCHITECTURE SUPPORT
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机译：混合式片上时钟控制器技术，可促进高速扫描测试和扫描架构支持
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摘要
Various aspects described or referenced herein are directed to different methods, systems, and computer program products for implementing hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support.
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