CONCURRENT TIMING-DRIVEN TOPOLOGY CONSTRUCTION AND BUFFERING FOR VLSI ROUTING

摘要

A system and method for topology construction for long and complex fan-out networks such as encountered in microprocessors include a modified Steiner tree algorithm with concurrent buffering to reduce post-buffer power/delay cost for a spanning tree. The system and method may prune Hanan points prior to calling a buffering tool to insert buffers and insert non-Hanan branching points. Embodiments may also include dividing a device into a plurality of super unit blocks, performing routing within each of the plurality of super units using a single crossing Steiner tree algorithm to determine a corresponding port, and aligning corresponding ports of each super unit to provide routing between the plurality of super units.