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Footer-less NP domino logic circuit and related apparatus
Footer-less NP domino logic circuit and related apparatus
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机译:无脚的NP多米诺骨牌逻辑电路及相关装置
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摘要
A domino logic circuit includes a pre-charge circuit pre-charging a first dynamic node in response to a clock signal, a first logic network determining a logic level of the first dynamic node in response to first data signals, an inverter receiving the clock signal, a discharge circuit discharging a second dynamic node in response to an output signal of the inverter, and a second logic network determining a logic level of the second dynamic node in response to at least one second data signal and an output signal of the first dynamic node.
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