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Method for optimizing memory controller placement in multi-core processors by determining a fitness metric based on a bottleneck link in a multiprocessor array
Method for optimizing memory controller placement in multi-core processors by determining a fitness metric based on a bottleneck link in a multiprocessor array
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机译:通过基于多处理器阵列中的瓶颈链接确定适应性度量来优化多核处理器中的存储控制器布局的方法
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摘要
The location of the memory controllers within the on-chip fabric of multiprocessor architectures plays a central role in latency bandwidth characteristics of the processor-to-memory traffic. Intelligent placement substantially reduces the maximum channel load depending on the specific memory controller configuration selected. A variety of simulation techniques are used along and in combination to determine optimal memory controller arrangements. Diamond-type and diagonal X-type memory controller configurations that spread network traffic across all rows and columns in a multiprocessor array substantially improve over other arrangements. Such placements reduce interconnect latency by an average of 10% for real workloads, and the small number of memory controllers relative to the number of on-chip cores opens up a rich design space to optimize latency and bandwidth characteristics of the on-chip network.
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